Package-on-package modules, electronic systems including the same, and memory cards including the same

ABSTRACT

Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a continuation of U.S. patent applicationSer. No. 14/254,768, filed Apr. 16, 2014, which claims priority under 35U.S.C 119(a) to Korean Application No. 10-2013-0159075, filed on Dec.19, 2013, in the Korean Intellectual Property Office, which isincorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to semiconductor packagesand, more particularly, to package-on-package modules, electronicsystems including the same, and memory cards including the same.

2. Related Art

With the development of electronics industry, faster, smaller and highperformance electronic components are increasingly in demand. Inresponse, semiconductor package technologies have been continuouslydeveloped. For example, a plurality of semiconductor chips may bestacked on a single package substrate to form multi-chip stackedpackages, or a plurality of semiconductor packages may be stacked toform package-on-package (PoP) modules. In the PoP modules, each of thestacked semiconductor packages may include a package substrate on whichat least one semiconductor chip is mounted. This may lead to adifficulty in reducing a thickness of the PoP modules.

To reduce a thickness of the PoP modules, each of the semiconductorpackages therein may be formed using a thin semiconductor chip. However,such semiconductor packages may readily warp. The warpage of thesemiconductor packages in the PoP modules may produce a stress inconnection members, such as solder balls, which provide electricalconnections between the semiconductor packages. As a result, cracks mayform at interfaces between the semiconductor packages and the connectionmembers, and the cracks may degrade the reliability of the PoP modules.

SUMMARY

Various embodiments are directed to package-on-package (PoP) modules,electronic systems including the same, and memory cards including thesame.

According to some embodiments, a package-on-package (PoP) moduleincludes a lower package and an upper package on the lower package. Thelower package includes a lower substrate and a lower chip disposed overa top surface of the lower substrate. The upper package includes anupper substrate, a plurality of upper chips disposed over a top surfaceof the upper substrate, and an upper molding member disposed over theplurality of upper chips. The upper molding member is divided into atleast two parts separated from each other by a trench.

According to further embodiments, a package-on-package (PoP) moduleincludes a lower package and upper package on the lower package. Thelower package includes a lower substrate and a lower chip disposed overa top surface of the lower substrate. The upper package includes anupper substrate, a plurality of upper chips disposed over a top surfaceof the upper substrate, and an upper molding member covering theplurality of upper chips. The upper molding member is divided into threeparts which are separated from each other by a first trench and a secondtrench. The first trench is located adjacent to a first side of theupper chips and the second trench is located adjacent to a second sideof the upper chips opposite to the first side.

According to further embodiments, a package-on-package (PoP) moduleincludes a lower package, an upper package and a supporting rib. Thelower package includes a lower substrate and a lower chip disposed overa top surface of the lower substrate. The upper package includes anupper substrate disposed over the lower chip, a plurality of upper chipsdisposed over a top surface of the upper substrate, and an upper moldingmember disposed over the plurality of upper chips. The supporting rib isattached to a bottom surface of the upper substrate and to sidewalls ofthe lower substrate.

According to further embodiments, an electronic system includes a memoryand a controller coupled with the memory. The memory or the controllerincludes a lower package and an upper package on the lower package. Thelower package includes a lower substrate and a lower chip disposed overa top surface of the lower substrate. The upper package includes anupper substrate, a plurality of upper chips disposed over a top surfaceof the upper substrate, and an upper molding member disposed over theplurality of upper chips. The upper molding member is divided into atleast two parts which are separated from each other by a trench.

According to further embodiments, an electronic system includes a memoryand a controller coupled with the memory. The memory or the controllerincludes a lower package and upper package on the lower package. Thelower package includes a lower substrate and a lower chip disposed overa top surface of the lower substrate. The upper package includes anupper substrate, a plurality of upper chips disposed over a top surfaceof the upper substrate, and an upper molding member covering theplurality of upper chips. The upper molding member is divided into threeparts which are separated from each other by a first trench and a secondtrench. The first trench is located at a first side of the upper chipsand the second trench is located at a second side of the upper chipsopposite to the first side.

According to further embodiments, an electronic system includes a memoryand a controller coupled with the memory. The memory or the controllerincludes a lower package, an upper package, and a supporting rib. Thelower package includes a lower substrate and a lower chip disposed overa top surface of the lower substrate. The upper package includes anupper substrate disposed over the lower chip, a plurality of upper chipsdisposed over a top surface of the upper substrate, and an upper moldingmember covering the plurality of upper chips. The supporting rib isattached to a bottom surface of the upper substrate and to sidewalls ofthe lower substrate.

According to further embodiments, a memory card includes a memory and amemory controller suitable for controlling an operation of the memory.The memory includes a lower package and an upper package on the lowerpackage. The lower package includes a lower substrate and a lower chipdisposed over a top surface of the lower substrate. The upper packageincludes an upper substrate, a plurality of upper chips disposed over atop surface of the upper substrate, and an upper molding member disposedover the plurality of upper chips. The upper molding member is dividedinto at least two parts which are separated from each other by a trench.

According to further embodiments, a memory card includes a memory and amemory controller suitable for controlling an operation of the memory.The memory includes a lower package and upper package on the lowerpackage. The lower package includes a lower substrate and a lower chipdisposed over a top surface of the lower substrate. The upper packageincludes an upper substrate, a plurality of upper chips disposed over atop surface of the upper substrate, and an upper molding member disposedover the plurality of upper chips. The upper molding member is dividedinto three parts which are separated from each other by a first trenchand a second trench. The first trench is located at a first side of theupper chips and the second trench is located at a second side of theupper chips opposite to the first side.

According to further embodiments, a memory card includes a memory and amemory controller suitable for controlling an operation of the memory.The memory includes a lower package, an upper package, and a supportingrib. The lower package includes a lower substrate and a lower chipattached to a top surface of the lower substrate. The upper packageincludes an upper substrate disposed over the lower chip, a plurality ofupper chips disposed over a top surface of the upper substrate, and anupper molding member disposed over the plurality of upper chips. Thesupporting rib is attached to a bottom surface of the upper substrateand to sidewalls of the lower substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will become more apparent in viewof the attached drawings and accompanying detailed description, inwhich:

FIG. 1 is a cross-sectional view illustrating a Package-on-Package (PoP)module according to an embodiment;

FIG. 2 is a perspective view illustrating a package suitable for use asthe upper package of the PoP module of FIG. 1;

FIG. 3 is a perspective view illustrating another package suitable foruse as the upper package of the PoP module of FIG. 1;

FIG. 4 is a perspective view illustrating another package suitable foruse as the upper package of the PoP module of FIG. 1;

FIG. 5 is a cross-sectional view illustrating a PoP module according toanother embodiment;

FIG. 6 is a perspective view illustrating a package suitable for use asthe upper package of the PoP module of FIG. 5;

FIG. 7 is a perspective view illustrating another package suitable foruse as the upper package of the PoP module of FIG. 5;

FIG. 8 is a cross-sectional view illustrating a PoP module according toanother embodiment;

FIG. 9 is a block diagram illustrating an electronic system including aPoP module according to an embodiment; and

FIG. 10 is a block diagram illustrating another electronic systemincluding a PoP module according to an embodiment.

DESCRIPTION OF SPECIFIC EMBODIMENTS

In a package-on-package (PoP) module including a lower package and anupper package which are electrically coupled to each other, connectionmembers electrically coupling the lower package to the upper package mayexperience various stresses. One cause of a stress to the connectionmembers is a difference between coefficients of thermal expansion of asubstrate and a molding member constituting the upper package.Embodiments of the present disclosure include PoP modules that mayreduce a stress applied to the connection members because of atemperature variation even though a coefficient of thermal expansion ofthe substrate is different from a coefficient of thermal expansion ofthe molding member. Even though the temperature variation is occurred,the extent of the bending moment by the warpage of the upper package isreduced, thereby reducing the stress applied to the connection members.Thus, the reliability of the PoP modules may be improved.

FIG. 1 is a cross-sectional view illustrating a package-on-package (PoP)module 10 according to an embodiment, and FIG. 2 is a perspective viewillustrating a package 200 suitable for use as an upper package 200 ofthe PoP module 10 of FIG. 1. FIG. 1 corresponds to a cross-sectionalview taken along a line I-I′ of FIG. 2.

The PoP module 10 includes a lower package 100 and an upper package 200disposed over the lower package 100. The lower package 100 may beelectrically coupled to and physically combined with the upper package200 through connection members 310. In an embodiment, the connectionmembers 310 may include solder balls. However, the connection members310 are not limited thereto, and in an embodiment, the connectionmembers 310 may include bumps.

The lower package 100 includes a lower substrate 110, a lower chip 120attached to a top surface of the lower substrate 110, and a lowermolding member 170 disposed over a portion of the lower substrate 110 tocover the lower chip 120. The lower substrate 110 may be a printedcircuit board (PCB) or a copper clad lamination, but is not limitedthereto. Although not shown in the drawings, various circuitinterconnection patterns may be disposed in and/or on the lowersubstrate 110.

Bonding pads 130 and connection pads 140 may be disposed on the topsurface of the lower substrate 110. External connection pads 150 may bedisposed on a bottom surface of the lower substrate 110 opposite to thebonding pads 130 and the connection pads 140. The arrangement of thebonding pads 130, the connection pads 140, and the external connectionpads 150 may depend on a layout scheme of the lower package 100.

The lower chip 120 may be attached to the top surface of the lowersubstrate 110 using an adhesive agent 122. The adhesive agent 122 mayinclude an insulation material such as an epoxy material. In someembodiments, the lower chip 120 may be a logic chip, for example, acontroller chip. Alternatively, the lower chip 120 may be a memory chipsuch as a dynamic random access memory (DRAM) chip or a flash memorychip. In addition, although FIG. 1 shows only one lower chip 120, anembodiment may include a plurality of chips disposed on or over thelower substrate 110 in the lower package 100.

First ends of conductive wires 160 may be connected to a top surface(e.g., contact pads) of the lower chip 120, and second ends of theconductive wires 160 opposite to the first ends may be connected to thebonding pads 130 disposed on the lower substrate 110. Thus, the lowerchip 120 may be electrically coupled to the lower substrate 110 throughthe conductive wires 160. The conductive wires 160 are suitable toelectrically connect the lower chip 120 and the lower substrate 110, butembodiments are not limited thereto. In another embodiment, the lowerchip 120 may be a flip chip that may be electrically coupled to thelower substrate 110 by an element other than the conductive wires 160,such as a solder bump, a conductive adhesive, or a built-up layer.

The lower chip 120, the conductive wires 160, and a portion of the lowersubstrate 110 may be covered with the lower molding member 170. Thebonding pads 130 may also be covered with the lower molding member 170.In contrast, the connection pads 140 may be left exposed by the lowermolding member 170. The lower molding member 170 may include an epoxymolding compound (EMC) material, but embodiments are not limitedthereto.

External connection members 180 may be attached to respective ones ofthe external connection pads 150. In an embodiment, the externalconnection members 180 may include solder balls, but embodiments are notlimited thereto. In another embodiment, the external connection members180 may include bumps.

The upper package 200 includes an upper substrate 210, a first upperchip 221 and a second upper chip 223 attached to a top surface of theupper substrate 210, and an upper molding member 270 disposed over thetop surface of the upper substrate 210 to cover the first and secondupper chips 221 and 223. The upper substrate 210 may be a PCB or acopper clad lamination, but embodiments are not limited thereto.Although not shown in the drawings, various circuit interconnectionpatterns may be disposed in or on the upper substrate 210.

First bonding pads 231 and second bonding pads 232 may be disposed onthe top surface of the upper substrate 210. External connection pads 250may be disposed on a bottom surface of the upper substrate 210 oppositeto the top surface. The arrangement of the first bonding pads 231, thesecond bonding pads 232, and the external connection pads 250 may dependon a layout scheme of the upper package 200. Connection members 310 maybe disposed between the connection pads 140 of the lower package 100 andthe external connection pads 250.

The first and second upper chips 221 and 223 are disposed to be spacedapart from each other along a first direction. In an embodiment, atleast one additional chip may be stacked over at least one of the firstand second upper chips 221 and 223.

The first upper chip 221 may be attached to a first region of the topsurface of the upper substrate 210 using a first adhesive agent 222. Thesecond upper chip 223 may be attached to a second region of the topsurface of the upper substrate 210 using a second adhesive agent 224.Each of the first and second adhesive agents 222 and 224 may include aninsulation material such as an epoxy material.

In an embodiment, the first and second upper chips 221 and 223 may bememory chips such as DRAM chips or flash memory chips, but embodimentsare not limited thereto. In an embodiment, the first and second upperchips 221 and 223 may be identical. In another embodiment, the first andsecond upper chips 221 and 223 may be different chips.

First ends of first conductive wires 261 may be connected to a topsurface (e.g., contact pads) of the first upper chip 221, and secondends of the first conductive wires 261 opposite to the first ends may beconnected to the first bonding pads 231 disposed on the upper substrate210. Thus, the first upper chip 221 may be electrically coupled to theupper substrate 210 through the first conductive wires 261.

The first conductive wires 261 are suitable for electrically couplingthe first upper chip 221 and the upper substrate 210, but embodimentsare not limited thereto. In another embodiment, the first upper chip 221may be a flip chip that may be electrically coupled to the uppersubstrate 210 by elements other than the first conductive wires 261.

First ends of second conductive wires 262 may be connected to a topsurface (e.g., contact pads) of the second upper chip 223, and secondends of the second conductive wires 262 opposite to the first ends maybe connected to the second bonding pads 232 disposed on the uppersubstrate 210. Thus, the second upper chip 223 may be electricallycoupled to the upper substrate 210 through the second conductive wires262.

The second conductive wires 262 are suitable for electrically couplingthe second upper chip 223 and the upper substrate 210, but embodimentsare not limited thereto. In an embodiment, the second upper chip 223 maybe a flip chip that may be electrically coupled to the upper substrate210 by elements other than the second conductive wires 262.

The first and second upper chips 221 and 223, the first and secondconductive wires 261 and 262 and the top surface of the upper substrate210 is covered with the upper molding member 270. The upper moldingmember 270 may include an EMC material, but embodiments are not limitedthereto.

The upper molding member 270 is divided into two parts by a trench 275.The trench 275 may be formed by removing a portion of the upper moldingmember 270 between the first and second upper chips 221 and 223. In anembodiment, the trench 275 exposes the upper substrate 210 between thefirst and second upper chips 221 and 223. The trench 275 divides theupper molding member 270 into a first upper molding member 271 coveringthe first upper chip 221 and the first conductive wires 261 and a secondupper molding member 272 covering the second upper chip 223 and thesecond conductive wires 262. That is, the first and second upper moldingmembers 271 and 272 may be separated from each other by the trench 275and may be arrayed in the first direction.

The trench 275 may extend in a second direction which is perpendicularto the first direction. In an embodiment, the trench 275 may be formedusing an appropriately configured molding frame in a molding processthat forms the first and second upper molding members 271 and 272. Inanother embodiment, the trench 275 may be formed by fabricating and thenmechanically sawing a single upper molding member.

Because the first and second upper molding members 271 and 272constituting the upper molding member 270 are separated by the trench275, stresses resulting from variance between coefficients of thermalexpansion may be reduced. For example, the trench 275 may reduce theextent of the bending moment by reducing the length of an individualbend or warp. For example, the length of a bending moment of eachmolding member 271 and 272 is less than a bending moment that wouldexist if trench 275 is not present to separate the molding members. Inaddition, trench 275 may provide a space which accepts expanded materialin the upper package 200. Furthermore, the trench 275 may provideventilation to the upper package and reduce its mass, thereby reducingthe rate of thermal expansion and the ultimate temperature experiencedby the module.

In FIGS. 3 and 4, the same reference numerals as used in FIGS. 1 and 2denote the same elements.

FIG. 3 illustrates another upper package 200-1 that may be employed inanother embodiment of the PoP module 10 of FIG. 1. The upper package200-1 includes an upper substrate 210, and an upper molding member 270and a buffer layer 281 disposed on the upper substrate 210. The uppermolding member 270 includes a first upper molding member 271 and asecond upper molding member 272 which are spaced apart from each otherin a first direction. The first and second upper molding members 271 and272 are separated from each other by a trench 275 extending in a seconddirection which is substantially perpendicular to the first direction.The first upper molding member 271 may cover a first upper chip 221, andthe second upper molding member 272 may cover a second upper chip 223.As described with reference to FIGS. 1 and 2, the trench 275 may exposethe upper substrate 210. The trench 275 may be filled with the bufferlayer 281.

When the temperature varies, the buffer layer 281 may relieve the stressgenerated between the first and second upper molding members 271 and272. For example, the buffer layer 281 may have a lower modulus than theupper molding material, so that buffer layer 281 deflects when moldingmembers 271 and 272 expand. In an embodiment, the buffer layer 281includes a polymeric material, for example polyimide or silicone.Sidewalls of the buffer layer 281 oriented in the first direction may besubstantially coplanar with sidewalls of the first and second uppermolding members 271 and 272, and a top surface of the buffer layer 281may be substantially coplanar with top surfaces of the first and secondupper molding members 271 and 272.

FIG. 4 illustrates another upper package 200-2 that may be employed inanother embodiment of the PoP module 10 of FIG. 1. The upper package200-2 includes an upper substrate 210-2, and first through fourth upperchips 225, 226, 227, and 228 two-dimensionally arrayed on the uppersubstrate 210-2 and spaced apart from each other. That is, the firstupper chip 225 and the second upper chip 226 may be spaced apart fromeach other in a first direction, the third upper chip 227 and the fourthupper chip 228 may also be spaced apart from each other in the firstdirection, the first upper chip 225 and the third upper chip 227 may bespaced apart from each other in a second direction which issubstantially perpendicular to the first direction, and the second upperchip 226 and the fourth upper chip 228 may also be spaced apart fromeach other in the second direction. The arrangement of the first throughfourth upper chips 225, 226, 227, and 228 may be different according tovarious embodiments.

First through fourth upper molding members 271-2, 272-2, 273-2, and274-2 are disposed on the upper substrate 210-2 and separated from eachother. The first, second, third and fourth upper molding members 271-2,272-2, 273-2, and 274-2 are disposed to cover the first, second, thirdand fourth upper chips 225, 226, 227, and 228, respectively.

The first and second upper molding members 271-2 and 272-2 may beseparated from each other by a first trench 276-1 extending in thesecond direction. The third and fourth upper molding members 273-2 and274-2 may also be separated from each other by the first trench 276-1.The first and third upper molding members 271-2 and 273-2 may beseparated from each other by a second trench 276-2 extending in thefirst direction. The second and fourth upper molding members 272-2 and274-2 may also be separated from each other by the second trench 276-2.

The first trench 276-1 may expose the upper substrate 210-2, and thesecond trench 276-2 may expose the upper substrate 210-2. In anembodiment, the first and second trenches 276-1 and 276-2 may be filledwith a buffer layer similar to that of the embodiment described withreference to FIG. 3.

FIGS. 5 and 6 illustrate a PoP module 20 according to anotherembodiment, with FIG. 5 illustrating a cross-sectional view taken alonga line II-II′ of FIG. 6. The PoP module 20 includes a lower package 400and an upper package 500 disposed over the lower package 400. The lowerpackage 400 may be electrically coupled to and physically connected withthe upper package 500 through connection members 610. The connectionmembers 610 may include solder balls, however, embodiments are notlimited thereto. In an embodiment, the connection members 610 includebumps.

The lower package 400 includes a lower substrate 410, a lower chip 420attached to a top surface of the lower substrate 410, and a lowermolding member 470 disposed over a portion of the lower substrate 410 tocover the lower chip 420. The lower substrate 410 may be a printedcircuit board (PCB) or a copper clad lamination, but embodiments are notlimited thereto. In an embodiment, various circuit interconnectionpatterns may be disposed in or on the lower substrate 410.

Bonding pads 430 and connection pads 440 may be disposed on the topsurface of the lower substrate 410. External connection pads 450 may bedisposed on a bottom surface of the lower substrate 410 opposite to thetop surface. The arrangement of the bonding pads 430, the connectionpads 440, and the external connection pads 450 may depend on a layoutscheme of the lower package 400.

The lower chip 420 may be attached to the top surface of the lowersubstrate 410 using an adhesive agent 422. The adhesive agent 422 mayinclude an insulation material such as an epoxy material. In anembodiment, the lower chip 420 may be a logic chip, for example, acontroller chip. In another embodiment, the lower chip 420 may be amemory chip such as a dynamic random access memory (DRAM) chip or aflash memory chip. Although FIG. 5 illustrates an embodiment includingonly one lower chip 420, embodiments are not limited thereto, and anembodiment may include a plurality of lower chips 420 stacked orotherwise disposed in the lower package 400.

First ends of conductive wires 460 may be connected to a top surface(e.g., contact pads) of the lower chip 420, and second ends of theconductive wires 460 opposite to the first ends may be connected to thebonding pads 430 disposed on the lower substrate 410. Thus, the lowerchip 420 may be electrically coupled to the lower substrate 410 throughthe conductive wires 460.

The conductive wires 460 are suitable for electrically coupling thelower chip 420 and the lower substrate 410, but embodiments are notlimited thereto. In an embodiment, the lower chip 420 may be a flip chipelectrically coupled to the lower substrate 410 by elements other thanthe conductive wires 460.

The lower chip 420, the conductive wires 460, and a portion of the lowersubstrate 410 may be covered with the lower molding member 470. Thebonding pads 430 may also be covered with the lower molding member 470.The connection pads 440 may be left exposed by the lower molding member470. The lower molding member 470 may include an epoxy molding compound(EMC) material, but embodiments are not limited thereto.

External connection members 480 may be attached to respective ones ofthe external connection pads 450. In an embodiment, the externalconnection members 480 may include solder balls, however, embodimentsare not limited thereto. In an embodiment, the external connectionmembers 480 may include bumps.

The upper package 500 includes an upper substrate 510, a first upperchip 521 and a second upper chip 523 disposed over a top surface of theupper substrate 510, and an upper molding member 570 disposed over thetop surface of the upper substrate 510 to cover the first and secondupper chips 521 and 523. The upper substrate 510 may be a PCB or acopper clad lamination, but embodiments are not limited thereto.Although not shown in the drawings, various circuit interconnectionpatterns may be disposed in or on the upper substrate 510.

Bonding pads 531 may be disposed on the top surface of the uppersubstrate 510. External connection pads 550 may be disposed on a bottomsurface of the upper substrate 510 opposite the top surface. Thearrangement of the bonding pads 531 and the external connection pads 550may depend on a layout scheme of the upper package 500. Connectionmembers 610 may be disposed between the connection pads 440 of the lowerpackage 400 and the external connection pads 550.

The first and second upper chips 521 and 523 may be sequentially stackedon the top surface of the upper substrate 510 in a vertical direction.The vertical direction means a direction which is perpendicular to thetop surface of the upper substrate 510. Although FIG. 5 illustrates anembodiment in which only two upper chips 521 and 523 are verticallystacked, embodiments are not limited thereto, and in an embodiment,three or more upper chips may be vertically stacked on the top surfaceof the upper substrate 510. In addition, a shape of the stacked upperchips may be different according to the embodiments. In an embodiment,the upper chips may be stacked to have a step structure.

The first upper chip 521 may be attached to the top surface of the uppersubstrate 510 using a first adhesive agent 522. The second upper chip523 may be attached to a top surface of the first upper chip 521 using asecond adhesive agent 524. Each of the first and second adhesive agents522 and 524 may include an insulation material such as an epoxymaterial. In an embodiment, the first and second upper chips 521 and 523may be memory chips such as DRAM chips or flash memory chips, butembodiments are not limited thereto.

First ends of first conductive wires 561 may be connected to a topsurface (e.g., contact pads) of the first upper chip 521, and secondends of the first conductive wires 561 opposite to the first ends may beconnected to the bonding pads 531 disposed on the upper substrate 510.Thus, the first upper chip 521 may be electrically coupled to the uppersubstrate 510 through the first conductive wires 561.

The first conductive wires 561 are suitable for electrically couplingthe first upper chip 521 and the upper substrate 510, but embodimentsare not limited thereto. In another embodiment, the first upper chip 521may be a flip chip and may be electrically coupled to the uppersubstrate 510 by elements other than the first conductive wires 561.

First ends of second conductive wires 562 may be connected to a topsurface (e.g., contact pads) of the second upper chip 523, and secondends of the second conductive wires 562 opposite to the first ends maybe connected to the bonding pads 531 disposed on the upper substrate510. Thus, the second upper chip 523 may be electrically coupled to theupper substrate 510 through the second conductive wires 562.

The first and second upper chips 521 and 523, the first and secondconductive wires 561 and 562, and the top surface of the upper substrate510 may be covered with the upper molding member 570. The upper moldingmember 570 may include an EMC material, but embodiments are not limitedthereto.

The upper molding member 570 may be divided into three parts by a firsttrench 575 and a second trench 576 which may be formed by removingportions of the upper molding member 570 located at both sides of thefirst and second upper chips 521 and 523. The first and second trenches575 and 576 may expose both edges of the upper substrate 510. As aresult, the first and second trenches 275 and 576 may separate the uppermolding member 570 into a first upper molding member 571 covering thefirst and second upper chips 521 and 523 and the first and secondconductive wires 561 and 562, a second upper molding member 572 locatedat a first side of the first upper molding member 571, and a third uppermolding member 573 located at a second side of the first upper moldingmember 571 opposite to the first side.

That is, the first and second upper molding members 571 and 572 may beseparated from each other by the first trench 575 and may be arranged ina first direction. The first trench 575 may extend in a second directionwhich is perpendicular to the first direction. The first and third uppermolding members 571 and 573 may be separated from each other by thesecond trench 576 and may be arranged in the first direction. The secondtrench 576 may extend in the second direction. Thus, the first andsecond trenches 575 and 576 may extend in the second direction.

A first width W1 of the second upper molding member 572 may be equal toa second width W2 of the third upper molding member 573, which mayresult in uniform thermal characteristics. In an embodiment, the firstand second trenches 575 and 576 may be formed using an appropriatelyconfigured molding frame in a molding process for forming the firstthrough third molding members 571, 572, and 573. In another embodiment,the first and second trenches 575 and 576 may be formed by fabricating asingle upper molding member and then mechanically sawing the singleupper molding member.

As described above, since the first through third upper molding members571, 572, and 573 constituting the upper molding member 570 areseparated by the first and second trenches 575 and 576, the thermalexpansion rate or the thermal shrinkage rate of each of the first tothird upper molding members 571, 572 and 573 may be reduced. Thus,stresses caused by differences in the coefficients of thermal expansionbetween the upper substrate 510 and the molding material may be reduced.

In FIG. 7, the same reference numerals as used in FIGS. 5 and 6 denotethe same elements. FIG. 7 illustrates another upper package 500-1 thatmay be employed in another embodiment of the PoP module 20 of FIG. 5.The upper package 500-1 includes an upper substrate 510, an uppermolding member 570, a first buffer layer 581, and a second buffer layer582 disposed over the upper substrate 510.

The upper molding member 570 includes a first upper molding member 571,a second upper molding member 572 and a third upper molding member 573which are spaced apart from each other in a first direction. The firstand second upper molding members 571 and 572 are separated from eachother by a first trench 575 extending in a second direction which issubstantially perpendicular to the first direction. The first and thirdupper molding members 571 and 573 are separated from each other by asecond trench 576 extending in the second direction. In an embodiment,the first upper molding member 571 covers a first upper chip 521 and asecond upper chip 523, as described with reference to FIGS. 5 and 6.

The first and second trenches 575 and 576 are filled with the firstbuffer layer 581 and the second buffer layer 582, respectively. When thetemperature varies, the first and second buffer layers 581 and 582relieve the stresses generated between the first through third uppermolding members 571, 572, and 573. In an embodiment, each of the firstand second buffer layers 581 and 582 may include a polymeric material.

Sidewalls of the first and second buffer layers 581 and 582 oriented inthe first direction may be substantially coplanar with sidewalls of thefirst through third upper molding members 571, 572, and 573 oriented inthe first direction, and top surfaces of the first and second bufferlayers 581 and 582 may be substantially coplanar with top surfaces ofthe first through third upper molding members 571, 572, and 573.

FIG. 8 illustrates a PoP module 30 according to another embodiment. ThePoP module 30 includes a lower package 700 and an upper package 800disposed over the lower package 700. The lower package 700 may beelectrically coupled to and physically connected with the upper package800 through connection members 910. In an embodiment, the connectionmembers 910 may include solder balls. However, embodiments are notlimited thereto, and in an embodiment, the connection members 910 mayinclude bumps.

A third width W3 of the lower package 700 may be less than a fourthwidth W4 of the upper package 800. Thus, both edges of the upper package800 may laterally protrude from both edges of the lower package 700 whenviewed from a cross-sectional view.

The lower package 700 includes a lower substrate 710, a lower chip 720attached to a top surface of the lower substrate 710, and a lowermolding member 770 disposed over a portion of the lower substrate 710 tocover the lower chip 720. The lower substrate 710 may be a printedcircuit board (PCB) or a copper clad lamination, but embodiments are notlimited thereto. Various circuit interconnection patterns may bedisposed in or on the lower substrate 710.

Bonding pads 730 and connection pads 740 may be disposed on the topsurface of the lower substrate 710. External connection pads 750 may bedisposed on a bottom surface of the lower substrate 710 opposite to thebonding pads 730 and the connection pads 740. The arrangement of thebonding pads 730, the connection pads 740, and the external connectionpads 750 may depend on a layout scheme of the lower package 700.

The lower chip 720 may be attached to the top surface of the lowersubstrate 710 using an adhesive agent 722. The adhesive agent 722 mayinclude an insulation material such as an epoxy material. In someembodiments, the lower chip 720 may be a logic chip, for example, acontroller chip. Alternatively, the lower chip 720 may be a memory chipsuch as a dynamic random access memory (DRAM) chip or a flash memorychip. FIG. 8 illustrates only one lower chip 720, but embodiments arenot limited thereto, and an embodiment may include a plurality of thelower chip 720 stacked or otherwise disposed over the lower substrate710.

First ends of conductive wires 760 may be connected to a top surface(e.g., contact pads) of the lower chip 720, and second ends of theconductive wires 760 opposite to the first ends may be connected to thebonding pads 730 disposed on the lower substrate 710. Thus, the lowerchip 720 may be electrically coupled to the lower substrate 710 throughthe conductive wires 760. The conductive wires 760 are suitable forelectrically coupling the lower chip 720 and the lower substrate 710,but embodiments are not limited thereto. In an embodiment, the lowerchip 720 may be a flip chip that may be electrically coupled to thelower substrate 710 by elements other than the conductive wires 760.

The lower chip 720, the conductive wires 760, and a portion of the lowersubstrate 710 may be covered by the lower molding member 770. Thebonding pads 730 may also be covered with the lower molding member 770.The connection pads 740 may be left exposed by the lower molding member770. The lower molding member 770 may include an epoxy molding compound(EMC) material, but embodiments are not limited thereto.

External connection members 780 may be attached to respective ones ofthe external connection pads 750. The external connection members 780may include solder balls, but embodiments are not limited thereto. In anembodiment, the external connection members 780 may include bumps.

The upper package 800 includes an upper substrate 810, a first upperchip 821 and a second upper chip 823 disposed over a top surface of theupper substrate 810, and an upper molding member 870 disposed over thetop surface of the upper substrate 810 to cover the first and secondupper chips 821 and 823. The upper substrate 810 may be a PCB or acopper clad lamination, but embodiments are not limited thereto. Variouscircuit interconnection patterns may be disposed in or on the uppersubstrate 810.

Bonding pads 831 may be disposed on the top surface of the uppersubstrate 810. External connection pads 850 may be disposed on a bottomsurface of the upper substrate 810 opposite to the top surface. Thearrangement of the bonding pads 831 and the external connection pads 850may depend on a layout scheme of the upper package 800. Connectionmembers 910 may be disposed between the connection pads 740 of the lowerpackage 700 and the external connection pads 850.

The first and second upper chips 821 and 823 may be sequentially stackedon the top surface of the upper substrate 810 in a vertical direction,that is, a direction which is perpendicular to the top surface of theupper substrate 810. Although FIG. 8 illustrates an embodiment in whichonly two upper chips 821 and 823 are vertically stacked, embodiments arenot limited thereto, and an embodiment may include three or more upperchips vertically stacked or otherwise disposed over the top surface ofthe upper substrate 810. In addition, a shape of the stacked upper chipsmay be different according to the embodiments. In an embodiment, theupper chips may be stacked to have a step structure.

The first upper chip 821 may be attached to the top surface of the uppersubstrate 810 using a first adhesive agent 822. The second upper chip823 may be attached to a top surface of the first upper chip 821 using asecond adhesive agent 824. Each of the first and second adhesive agents822 and 824 may include an insulation material such as an epoxymaterial.

In some embodiments, the first and second upper chips 821 and 823 may bememory chips such as DRAM chips or flash memory chips, but embodimentsare not limited thereto.

First ends of first conductive wires 861 may be connected to a topsurface (e.g., contact pads) of the first upper chip 821, and secondends of the first conductive wires 861 opposite to the first ends may beconnected to the bonding pads 831 disposed on the upper substrate 810.Thus, the first upper chip 821 may be electrically coupled to the uppersubstrate 810 through the first conductive wires 861.

The first conductive wires 861 are suitable for electrically couplingthe first upper chip 821 and the upper substrate 810, but embodimentsare not limited thereto. In an embodiment, the first upper chip 821 maybe a flip chip and may be electrically coupled to the upper substrate810 using an element other than the first conductive wires 861.

First ends of second conductive wires 862 may be connected to a topsurface (e.g., contact pads) of the second upper chip 823, and secondends of the second conductive wires 862 opposite to the first ends maybe connected to the bonding pads 831 disposed on the upper substrate510. Thus, the second upper chip 823 may be electrically coupled to theupper substrate 810 through the second conductive wires 862.

The first and second upper chips 821 and 823, the first and secondconductive wires 861 and 862, and the top surface of the upper substrate810 may be covered with the upper molding member 870. The upper moldingmember 870 may include an EMC material, but embodiments are not limitedthereto.

A supporting rib 920 is attached to the bottom surface of the uppersubstrate 810 and to sidewalls of the lower substrate 710 and maysurround the lower molding member 770 and the connection members 910. Inan embodiment, the supporting rib 920 may be attached to the bottomsurface of the upper substrate 810 using a third adhesive agent 931 andmay be attached to the sidewalls of the lower substrate 710 using afourth adhesive agent 932. In an embodiment, the supporting rib 920 maybe a solder dam. Although FIG. 8 shows two supporting ribs 920 runningin the second direction, two more ribs 920 running along the firstdirection and also acting as solder dams may be present. Otherembodiments may include a plurality of ribs 920 arranged in one or moredirection to resist warpage.

If In an embodiment, a coefficient of thermal expansion of the uppermolding member 870 is different from a coefficient of thermal expansionof the upper substrate 810. Such a difference between the thermalexpansion coefficients of the upper molding member 870 and the uppersubstrate 810 may cause warpage of the upper package 800 when thetemperature varies, producing a stress on the connection members 910which may cause connection failures between the lower package 700 andthe upper package 800.

However, the supporting rib 920 disposed between the upper package 800and the lower package 700 suppresses warpage of the upper package 800when the coefficient of thermal expansion of the upper molding member870 is different from the coefficient of thermal expansion of the uppersubstrate 810. The supporting rib 920 may therefore reduce a stressapplied to the connection members 910. Thus, the supporting rib 920 mayreduce the occurrence of connection failures between the lower package700 and the upper package 800.

The PoP modules described above may be applied to various electronicsystems.

Referring to FIG. 9, a PoP module in accordance with an embodiment maybe applied to an electronic system 1710. The electronic system 1710 mayinclude a controller 1711, an input/output device 1712, and a memory1713. The controller 1711, the input/output device 1712, and the memory1713 may be coupled with one another through a bus 1715 providing a paththrough which data are transmitted.

In an embodiment, the controller 1711 may include at least one of amicroprocessor, a digital signal processor, a microcontroller, and logicdevices capable of performing the same functions as these components. Atleast one of the controller 1711 and the memory 1713 may include atleast one of the PoP modules according to an embodiment of the presentdisclosure. The input/output device 1712 may include at least oneselected among a keypad, a keyboard, a display device, a touch screenand so forth. The memory 1713 includes a device for storing data. Thememory 1713 may store data and/or commands to be executed by thecontroller 1711, and the likes.

The memory 1713 may include a volatile memory device such as a DRAMand/or a nonvolatile memory device such as a flash memory. In anembodiment, a flash memory may be mounted to an information processingsystem such as a mobile terminal or a desk top computer. The flashmemory may constitute a solid state disk (SSD), and the electronicsystem 1710 may stably store a large amount of data in the flash memory.

The electronic system 1710 may further include an interface 1714suitable for transmitting and receiving data to and from a communicationnetwork. The interface 1714 may be a wired or wireless type, and mayinclude an antenna or a wired or wireless transceiver.

The electronic system 1710 may be realized as a mobile system, apersonal computer, an industrial computer, or a logic system performingvarious functions. For example, the mobile system may be any one of apersonal digital assistant (PDA), a portable computer, a tabletcomputer, a mobile phone, a smart phone, a wireless phone, a laptopcomputer, a memory card, a digital music system, and an informationtransmission/reception system.

In the case where the electronic system 1710 is an equipment capable ofperforming wireless communication, the electronic system 1710 may beused in a communication system such as of CDMA (code division multipleaccess), GSM (global system for mobile communications), NADC (northAmerican digital cellular), E-TDMA (enhanced-time division multipleaccess), WCDMA (wideband code division multiple access), CDMA2000, LTE(long term evolution) and Wibro (wireless broadband Internet).

Referring to FIG. 10, a PoP module in accordance with an embodiment maybe provided in a memory card 1800. For example, the memory card 1800 mayinclude a memory 1810 such as a nonvolatile memory device and a memorycontroller 1820. The memory 1810 and the memory controller 1820 maystore data or read stored data.

The memory 1810 may include at least one nonvolatile memory device inwhich the PoP modules according to the embodiments are employed. Thememory controller 1820 may control the memory 1810 such that stored datais read out or data is stored in response to a read/write request from ahost 1830.

Embodiments have been disclosed for illustrative purposes. Those skilledin the art will appreciate that various modifications, additions, andsubstitutions are possible, without departing from the scope and spiritof the present disclosure and the accompanying claims.

What is claimed is:
 1. A package-on-package (PoP) module comprising: alower package including a lower substrate, a lower chip disposed over atop surface of the lower substrate, and a lower molding member coveringthe lower chip; and an upper package disposed over the lower moldingmember of the lower package, wherein the upper package includes an uppersubstrate, a plurality of upper chips laterally disposed over a topsurface of the upper substrate, and an upper molding member entirelycovering the plurality of upper chips, wherein the upper molding memberis divided into at least two parts separated from each other by atrench, and wherein the trench exposed the top surface of the uppersubstrate.
 2. The PoP module of claim 1, further comprising a connectionmember disposed between the lower substrate and the upper substrate. 3.The PoP module of claim 2, wherein the connection member includes asolder ball.
 4. The PoP module of claim 1, wherein the plurality ofupper chips are spaced apart from each other and are arranged in a firstdirection.
 5. The PoP module of claim 4, wherein the trench extends in asecond direction which is substantially perpendicular to the firstdirection.
 6. The PoP module of claim 1, further comprising a bufferlayer disposed within the trench.
 7. The PoP module of claim 6, whereinthe buffer layer includes a polymeric material.
 8. The PoP module ofclaim 6, wherein a surface of the buffer layer and a surface of thedivided upper molding member are coplanar.
 9. The PoP module of claim 1,wherein the plurality of upper chips are spaced apart from each otherand are two dimensionally arrayed along first and second directions. 10.The PoP module of claim 9, wherein the first and second directions aresubstantially perpendicular to each other.
 11. The PoP module of claim9, wherein the trench includes a first trench located between two of theplurality of upper chips and a second trench located between two of theplurality of upper chips; and wherein the first trench and the secondtrench are oriented in the second direction and the first direction,respectively.